HD6432351 datasheet(117/1025 Pages) RENESAS

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Section 4 Exception Handling

Rev. 3.00 Sep 15, 2006 page 83 of 988

REJ09B0330-0300

4.2.3

Reset Sequence

The H8S/2350 Group enters the reset state when the

RES pin goes low.

To ensure that the H8S/2350 Group is reset, hold the

RES pin low for at least 20 ms at power-up.

To reset the H8S/2350 Group during operation, hold the

RES pin low for at least 20 states.

When the

RES pin goes high after being held low for the necessary time, the H8S/2350 Group

starts reset exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figures 4.2 and 4.3 show examples of the reset sequence.

Internal

address bus

Internal read

signal

Internal write

signal

Internal data

bus

(1)

(3)

Vector

fetch

Internal

processing

Prefetch of first program

instruction

High

(1) Reset exception handling vector address ((1) = H'0000)

(2) Start address (contents of reset exception handling vector address)

(3) Start address ((3) = (2))

(4) First program instruction

(2)

(4)

RES

Figure 4.2 Reset Sequence (Modes 2 and 3)

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