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HD6432351 bảng dữ liệu(PDF) 928 Page - Renesas Technology Corp |
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HD6432351 bảng dữ liệu(HTML) 928 Page - Renesas Technology Corp |
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928 / 1025 page ![]() Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 894 of 988 REJ09B0330-0300 SCR0—Serial Control Register 0 H'FF7A Smart Card Interface 0 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 0 CKE0 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W SMCR SMIF 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 SMR C/ A,GM CKE1 CKE0 See SCI specification SCK pin function Clock Enable SCR setting 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Transmit End Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor Interrupt Enable 0 1 Reception disabled Reception enabled Receive Enable 0 1 Transmission disabled Transmission enabled Transmit Enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Transmit Interrupt Enable Bit Initial value Read/Write : : : Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin |
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