HD6432351 datasheet(651/1025 Pages) RENESAS

651 / 1025 page

Section 14 Smart Card Interface

Rev. 3.00 Sep 15, 2006 page 617 of 988

REJ09B0330-0300

Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the

error signal sent back from the receiving end in transmission. Framing errors are not detected in

Smart Card interface mode.

Bit 4

ERS

Description

Indicates that data was received normally and no error signal was sent

[Clearing conditions]

(Initial value)

• Upon reset, and in standby mode or module stop mode

• When 0 is written to ERS after reading ERS = 1

Indicates that an error signal was sent from the receiving side showing that a parity

error was detected

[Setting condition]

When the low level of the error signal is sampled

Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous

state.

Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial

Status Register (SSR).

However, the setting conditions for the TEND bit, are as shown below.

Bit 2

TEND

Description

Indicates data transmission in progress

[Clearing conditions]

(Initial value)

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR

Indicates that data transmission in finished

[Setting conditions]

• Upon reset, and in standby mode or module stop mode

• When the TE bit in SCR is 0 and the ERS bit is also 0

• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a

1-byte serial character when GM = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1

Note: etu: Elementary Time Unit (time for transfer of 1 bit)

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