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HD6432351 bảng dữ liệu(PDF) 537 Page - Renesas Technology Corp

tên linh kiện HD6432351
Giải thích chi tiết về linh kiện  16-Bit Single-Chip Microcomputer
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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HD6432351 bảng dữ liệu(HTML) 537 Page - Renesas Technology Corp

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Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep 15, 2006 page 503 of 988
REJ09B0330-0300
Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10.57 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1
T2
H'FFFF
M
TCNT write data
TCFV flag
Figure 10.57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins
In the H8S/2350 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the
TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and
the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match
output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore
be disabled before entering module stop mode.



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