HD6432351 datasheet(461/1025 Pages) RENESAS

461 / 1025 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 427 of 988

REJ09B0330-0300

10.2.3

Timer I/O Control Register (TIOR)

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

R/W

Channel 0: TIOR0H

Channel 1: TIOR1

Channel 2: TIOR2

Channel 3: TIOR3H

Channel 4: TIOR4

Channel 5: TIOR5

IOD3

R/W

IOD2

R/W

IOD1

R/W

IOD0

R/W

IOC3

R/W

IOC0

R/W

IOC2

R/W

IOC1

R/W

Channel 0: TIOR0L

Channel 3: TIOR3L

Note:

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the

Bit

Initial value

R/W

The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR

registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR

registers are initialized to H'00 by a reset, and in hardware standby mode.

Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR

is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM

mode 2, the output at the point at which the counter is cleared to 0 is specified.

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