HD6432351 datasheet(422/1025 Pages) RENESAS

422 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 388 of 988

REJ09B0330-0300

9.11.2

Table 9.19 shows the port D register configuration.

Table 9.19 Port D Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port D data direction register

PDDDR

H'00

H'FEBC

Port D data register

PDDR

R/W

H'00

H'FF6C

Port D register

PORTD

Undefined

H'FF5C

Port D MOS pull-up control register

PDPCR

R/W

H'00

H'FF73

Note:

* Lower 16 bits of the address.

Port D Data Direction Register (PDDDR) [H8S/2351 Only]

PD7DDR

PD6DDR

PD5DDR

PD4DDR

PD3DDR

PD0DDR

PD2DDR

PD1DDR

Bit

Initial value

R/W

PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port D. PDDDR cannot be read; if it is, an undefined value will be read..

PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its

prior state after a manual reset, and in software standby mode.

• Modes 1, 2, and 4 to 6

The input/output direction specification by PDDDR is ignored, and port D is automatically

designated for data I/O.

• Modes 3 and 7

Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing

the bit to 0 makes the pin an input port.

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