H838532H datasheet(276/508 Pages) RENESAS

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Section 9 Timers

Rev. 1.00 May 30, 2008 Page 256 of 484

REJ09B0436-0100

b. Interval timer operation

When the TMIG bit is cleared to 0 in PMR1, timer G functions as an interval timer. Following

a reset, TCG starts incrementing on the

φ/64 internal clock. The input clock can be selected

from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments on the

selected clock, and when it overflows from H’FF to H’00, the OVFL bit is set to 1 in TMG. If

the OVIE bit in TMG is 1 at this time, IRRTG is set to 1 in IRR2, and if the IENTG bit in

IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see

section 3.3, Interrupts.

(2) Increment Timing

TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four

internal clock sources (

φ/64, φ/32, φ/2, or φw/4) created by dividing the system clock (φ) or watch

clock (

φw).

(3) Input Capture Input Timing

a. Without noise cancellation function

For input capture input, dedicated input capture functions are provided for rising and falling

edges.

Figure 9.11 shows the timing for rising/falling edge input capture input.

Input capture

input signal

Input capture

signal F

Input capture

signal R

Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function)

b. With noise cancellation function

When noise cancellation is performed on the input capture input, the passage of the input

capture signal through the noise canceler results in a delay of five sampling clock cycles from

the input capture input signal edge.

Figure 9.12 shows the timing in this case.

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