H838532H datasheet(262/508 Pages) RENESAS

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Section 9 Timers

Rev. 1.00 May 30, 2008 Page 242 of 484

REJ09B0436-0100

b. TCFL, OCRFL

In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write

by a MOV instruction and generation of the compare match signal occur simultaneously,

TOLL data is output to the TMOFL pin as a result of the TCRF write.

If an OCRFL write and compare match signal generation occur simultaneously, the compare

match signal is invalid. However, if the written data and the counter value match, a compare

match signal will be generated at that point. As the compare match signal is output in

synchronization with the TCFL clock, a compare match will not result in compare match

signal generation if the clock is stopped.

If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not

output.

(3) Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL),

Timer Overflow Flags H, L (OVFH, OVFL) and Compare Match Flags H, L

(CMFH, CMFL)

When

φw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated

with

φw and the signal will be outputted with φw width. And, “Overflow signal” and “Compare

match signal” are controlled with 2 cycles of

φw signals. Those signals are outputted with 2 cycles

width of

φw (figure 9.7)

In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the

term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure

9.7 (1)) And, you cannot be cleared timer overflow flag and compare match flag during the term

of validity of “Overflow signal” and “Compare match signal”.

For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time

timer FH, timer FL interrupt might be repeated. (figure 9.7 (2)) Therefore, to definitely clear

interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after

the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and

compare match flag, clear should be processed after read timer control status register F (TCSRF)

after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the

longest number of execution states in used instruction. (10 states of RTE instruction when

MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In

subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and

compare match flag clear.

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