H838532H datasheet(248/508 Pages) RENESAS

248 / 508 page

Section 9 Timers

Rev. 1.00 May 30, 2008 Page 228 of 484

REJ09B0436-0100

When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If

OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if

IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.

(2) 16-bit Output Compare Register (OCRF)

8-bit Output Compare Register (OCRFH)

8-bit Output Compare Register (OCRFL)

OCRF

OCRFH

OCRFL

76543210

1111111111111111

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit

Initial value

Read/Write

OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In

addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as

the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.

OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,

data transfer to and from the CPU is performed via a temporary register (TEMP). For details of

TEMP, see section 9.4.3, CPU Interface.

OCRFH and OCRFL are each initialized to H'FF upon reset.

a. 16-bit mode (OCRF)

When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are

constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At

the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt

request is sent to the CPU.

Toggle output can be provided from the TMOFH pin by means of compare matches, and the

output level can be set (high or low) by means of TOLH in TCRF.

b. 8-bit mode (OCRFH/OCRFL)

When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit

registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL.

When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in

TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in

IENR2 is 1 at this time, an interrupt request is sent to the CPU.

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