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H838532H bảng dữ liệu(PDF) 365 Page - Renesas Technology Corp |
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H838532H bảng dữ liệu(HTML) 365 Page - Renesas Technology Corp |
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365 / 508 page ![]() Section 11 14-Bit PWM Rev. 1.00 May 30, 2008 Page 345 of 484 REJ09B0436-0100 When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should always be written in the following sequence: 1. Write the lower 8 bits to PWDRL. 2. Write the upper 6 bits to PWDRU. PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1. Upon reset, PWDRU and PWDRL are initialized to H'C000. 11.2.3 Clock Stop Register 2 (CKSTPR2) — WDCKSTP PWCKSTP LDCKSTP — — — AECKSTP 7 6543210 1 1111111 — R/W R/W R/W ——— R/W Bit Initial value Read/Write CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the PWM is described here. For details of the other bits, see the sections on the relevant modules. Bit 1: PWM module standby mode control (PWCKSTP) Bit 1 controls setting and clearing of module standby mode for the PWM. PWCKSTP Description 0 PWM is set to module standby mode 1 PWM module standby mode is cleared (initial value) |
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