H838532H datasheet(354/508 Pages) RENESAS

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Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 334 of 484

REJ09B0436-0100

10.4

Interrupts

SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and

three receive error interrupts (overrun error, framing error, and parity error). These interrupts have

the same vector address.

The various interrupt requests are shown in table 10.13.

Table 10.13 SCI3 Interrupt Requests

Interrupt Abbr. Interrupt Request

Vector Address

RXI

Interrupt request initiated by receive data full flag (RDRF)

H'0022/H'0024

TXI

Interrupt request initiated by transmit data empty flag (TDRE)

TEI

Interrupt request initiated by transmit end flag (TEND)

ERI

Interrupt request initiated by receive error flag

(OER, FER, PER)

Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.

When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in

SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.

The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request

(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI

interrupt will be requested even if the transmit data is not ready.

Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request

(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI

interrupt will be requested even if the transmit data has not been sent.

Effective use of these interrupt requests can be made by having processing that transfers transmit

data to TDR carried out in the interrupt service routine.

To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable

bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been

transferred to TDR.

When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and

FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during

reception.

For further details, see section 3.3, Interrupts.

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