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H838532H bảng dữ liệu(PDF) 337 Page - Renesas Technology Corp |
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H838532H bảng dữ liệu(HTML) 337 Page - Renesas Technology Corp |
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337 / 508 page ![]() Section 10 Serial Communication Interface Rev. 1.00 May 30, 2008 Page 317 of 484 REJ09B0436-0100 10.3.2 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. (1) Data Transfer Format The general data transfer format in asynchronous communication is shown in figure 10.3. Serial data Start bit 1 bit Transmit/receive data Parity bit Stop bit(s) 5, 7, or 8 bits One transfer data unit (character or frame) 1 bit or none 1 or 2 bits Mark state 1 (MSB) (LSB) Figure 10.3 Data Format in Asynchronous Communication In asynchronous communication, the communication line is normally in the mark state (high level). SCI3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. One transfer data character consists of a start bit (low level), followed by transmit/receive data (LSB-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). |
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