38K0 datasheet(13/328 Pages) RENESAS

13 / 328 page

Rev.2.00

Oct 05, 2006

page 9 of 13

38K0 Group

REJ09B0337-0200

Fig. 2.10.5 Block diagram for frequency synthesizer circuit ..................................................... 85

Fig. 2.10.6 Related registers setting when hardware reset ...................................................... 86

Fig. 2.10.7 Related registers setting when stop mode .............................................................. 87

Fig. 2.10.8 Related registers setting when recovery from stop mode .................................... 88

Fig. 2.11.1 Memory map of registers related to clock generating circuit ............................... 89

Fig. 2.11.2 Structure of USB control register ............................................................................. 89

Fig. 2.11.3 Structure of CPU mode register ............................................................................... 90

Fig. 2.11.4 Structure of PLL control register .............................................................................. 90

Fig. 2.11.5 Related registers setting ............................................................................................ 91

Fig. 2.11.6 Related registers setting ............................................................................................ 93

Fig. 2.12.1 Memory map of registers related to standby function ........................................... 94

Fig. 2.12.2 Structure of MISRG .................................................................................................... 94

Fig. 2.12.3 Oscillation stabilizing time at restoration by reset input ....................................... 96

Fig. 2.12.4 Execution sequence example at restoration by occurrence of INT0 interrupt request

...................................................................................................................................... 98

Fig. 2.12.5 Reset input time ........................................................................................................ 100

Fig. 2.13.1 Memory map of flash memory version for 38K0 Group ...................................... 102

Fig. 2.13.2 Memory map of registers related to flash memory .............................................. 103

Fig. 2.13.3 Structure of Flash memory control register ........................................................... 103

Fig. 2.13.4 Rewrite example of built-in flash memory in standard serial I/O mode ............ 106

Fig. 2.13.5 Connection example in standard serial I/O mode (1) .......................................... 107

Fig. 2.13.6 Connection example in standard serial I/O mode (2) .......................................... 107

Fig. 2.13.7 Connection example in standard serial I/O mode (3) .......................................... 108

Fig. 2.13.8 Example of rewrite system for built-in flash memory in CPU rewrite mode .... 109

Fig. 2.13.9 CPU rewrite mode beginning/release flowchart .................................................... 110

CHAPTER 3 APPENDIX

Fig. 3.1.1 Output switching characteristics measurement circuit ............................................. 11

Fig. 3.1.2 USB output switching characteristics measurement circuit (1) for D0- ................. 13

Fig. 3.1.3 USB output switching characteristics measurement circuit (2) for D0+ ................ 13

Fig. 3.1.4 Timing chart (1) ............................................................................................................. 14

Fig. 3.1.5 Timing chart (2) ............................................................................................................. 15

Fig. 3.1.6 Timing chart (3) ............................................................................................................. 16

Fig. 3.1.7 Timing chart (4) ............................................................................................................. 17

Fig. 3.1.8 Timing chart (5) ............................................................................................................. 18

Fig. 3.1.9 Timing chart (6) ............................................................................................................. 19

Fig. 3.2.1 Sequence of changing relevant register .................................................................... 22

Fig. 3.2.2 Sequence of check of interrupt request bit ............................................................... 23

Fig. 3.2.3 Sequence of setting serial I/O control register again .............................................. 25

Fig. 3.2.4 Initialization of processor status register ................................................................... 29

Fig. 3.2.5 Sequence of PLP instruction execution ..................................................................... 29

Fig. 3.2.6 Stack memory contents after PHP instruction execution ........................................ 29

Fig. 3.2.7 Status flag at decimal calculations ............................................................................. 30

Fig. 3.3.1 Selection of packages .................................................................................................. 32

Fig. 3.3.3 Wiring for clock I/O pins .............................................................................................. 33

Fig. 3.3.4 Wiring for CNVSS pin ..................................................................................................... 33

Fig. 3.3.5 Wiring for the VPP pin of the flash memory version ................................................. 34

Fig. 3.3.6 Bypass capacitor across the VSS line and the VCC line ........................................... 34

Fig. 3.3.7 Analog signal line and a resistor and a capacitor ................................................... 35

Fig. 3.3.8 Wiring for a large current signal line ......................................................................... 36

___________

Fig. 3.3.9 Wiring of RESET pin .................................................................................................... 36

Fig. 3.3.10 VSS pattern on the underside of an oscillator ......................................................... 37

List of figures

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