SH7672 datasheet(16/1292 Pages) RENESAS

16 / 1292 page

Rev. 1.00 Nov. 14, 2007 Page xvi of xxvi

12.6

Usage Notes ...................................................................................................................... 436

Section 13

Ethernet Controller Direct Memory

Access Controller (E-DMAC)........................................................ 437

13.1

Features............................................................................................................................. 437

13.2

Register Descriptions........................................................................................................ 438

13.2.1

E-DMAC Mode Register (EDMR) ................................................................... 439

13.2.2

E-DMAC Transmit Request Register (EDTRR) .............................................. 441

13.2.3

E-DMAC Receive Request Register (EDRRR)................................................ 442

13.2.4

Transmit Descriptor List Address Register (TDLAR)...................................... 443

13.2.5

Receive Descriptor List Address Register (RDLAR) ....................................... 444

13.2.6

EtherC/E-DMAC Status Register (EESR) ........................................................ 445

13.2.7

EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) ................... 450

13.2.8

Transmit/Receive Status Copy Enable Register (TRSCER)............................. 453

13.2.9

Receive Missed-Frame Counter Register (RMFCR) ........................................ 455

13.2.10

Transmit FIFO Threshold Register (TFTR)...................................................... 456

13.2.11

FIFO Depth Register (FDR) ............................................................................. 457

13.2.12

Receiving Method Control Register (RMCR) .................................................. 458

13.2.13

E-DMAC Operation Control Register (EDOCR) ............................................. 459

13.2.14

Receiving-Buffer Write Address Register (RBWAR) ...................................... 460

13.2.15

Receiving-Descriptor Fetch Address Register (RDFAR) ................................. 461

13.2.16

Transmission-Buffer Read Address Register (TBRAR)................................... 461

13.2.17

Transmission-Descriptor Fetch Address Register (TDFAR) ............................ 462

13.2.18

Flow Control FIFO Threshold Register (FCFTR) ............................................ 462

13.2.19

Receive Data Padding Setting Register (RPADIR) .......................................... 464

13.2.20

Transmit Interrupt Register (TRIMD) .............................................................. 465

13.2.21

Checksum Mode Register (CSMR) .................................................................. 465

13.2.22

Checksum Skipped Bytes Monitor Register (CSSBM ) ................................... 467

13.2.23

Checksum Monitor Register (CSSMR) ............................................................ 468

13.3

Operation .......................................................................................................................... 469

13.3.1

Descriptor List and Data Buffers ...................................................................... 469

13.3.2

Transmission..................................................................................................... 481

13.3.3

Reception .......................................................................................................... 483

13.3.4

Multi-Buffer Frame Transmit/Receive Processing ........................................... 485

13.3.5

Padding Receive Data....................................................................................... 487

13.3.6

Checksum Calculation Function ....................................................................... 488

13.3.7

Usage Notes ...................................................................................................... 491

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