H83802 datasheet(21/555 Pages) RENESAS

21 / 555 page

Rev. 6.00 Mar 15, 2005 page xxi of l

Item

Page

Revisions (See Manual for Details)

9.4.6 Usage Notes

248, 249 Description amended

2. The maximum clock frequency that may be input to the

AEVH and AEVL pins is 16 MHz*

1. Furthermore, the clock

high width and low width should be half or more the OSC

clock cycle time. The duty ratio does not matter as long as

the high width and low width satisfy the minimum

requirement.

Mode

Maximum Clock

Frequency Input to

AEVH/AEVL Pin

Watch, subactive, subsleep, standby

φW = 32.768 kHz or 38.4 kHz*2

(

φW/2)

(

φW/4)

(

φW/8)

1000 kHz

500 kHz

250 kHz

Notes: 1.

Up to 10 MHz in the H8/38004, H8/38002S Group.

Does not apply to H8/38104 Group.

9.5 Watchdog Timer

250

Description amended

However, as shown in watchdog timer block diagrams figure

9.12 (1) and figure 9.12 (2), the implementation differs in the

H8/38004, H8/38002S Group and the H8/38104 Group.

9.5.1 Features

Description amended

• Selectable from two counter input clocks (H8/38004,

H8/38002S Group).

Figure 9.12(1) Block

Diagram of Watchdog

Timer (H8/38004,

H8/38002S Group)

Title amended

9.5.2 Register

Descriptions

Timer Control/Status

253

Notes amended

Notes: 2.Initial value 0 on H8/38004, H8/38002S Group and 1

on H8/38104 Group.

3.On reset, cleared to 0 on H8/38004, H8/38002S Group

and set to 1 on H8/38104 Group.

9.5.3 Operation

254

Description amended

The input clock is selected by the WDCKS bit in the port mode

φ/8192 is selected when the WDCKS bit is cleared to 0, and

φw/32 when set to 1.

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