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R8C2K bảng dữ liệu(PDF) 329 Page - Renesas Technology Corp |
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R8C2K bảng dữ liệu(HTML) 329 Page - Renesas Technology Corp |
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329 / 471 page ![]() R8C/2K Group, R8C/2L Group 16. Timers Rev.1.10 Dec 21, 2007 Page 312 of 450 REJ09B0406-0110 • If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1, in that order, when changing from increment to decrement operation. When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR register are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to registers such as the TRDGRA0 register. Figure 16.147 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode No change IMFA bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Count value in TRD0 register Setting value in TRDGRA0 register m m+1 Set to 0 by a program Not transferred from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 11b (transfer from the buffer register to the general register at compare match of between registers TRD0 and TRDGRA0). 1 0 |
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