R8C2K datasheet(291/471 Pages) RENESAS

291 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 274 of 450

REJ09B0406-0110

Figure 16.114 TRDFCR Register in Reset Synchronous PWM Mode

Timer RD Function Control Register

Symbol

Address

After Reset

TRDFCR

013Ah

10000000b

Bit Symbol

Bit Name

Function

NOTES:

3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is

enabled.

b3 b2

OLS1

b1 b0

b7 b6 b5 b4

CMD1

Combination mode select bits(1, 2)

Set to 01b (reset synchronous PWM

mode) in reset synchronous PWM mode.

CMD0

Normal-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

0 : Initial output “H”

Active level “L”

1 : Initial output “L”

Active level “H”

Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).

OLS0

Counter-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

0 : Initial output “H”

Active level “L”

1 : Initial output “L”

Active level “H”

A/D trigger enable bit

(in complementary PWM mode)

This bit is disabled in reset synchronous

PWM mode.

PWM3

ADTRG

ADEG

A/D trigger edge select bit

(in complementary PWM mode)

This bit is disabled in reset synchronous

PWM mode.

PWM3 mode select bit(3)

This bit is disabled in reset synchronous

PWM mode.

When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or

complementary PWM mode in spite of the setting of the TRDPMR register.

STCLK

External clock input select bit

0 : External clock input disabled

1 : External clock input enabled

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