R8C2K datasheet(257/471 Pages) RENESAS

257 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 240 of 450

REJ09B0406-0110

16.4.5.1

Digital Filter

The TRDIOji input is sampled, and when the sampled input level matches 3 times, its level is determined.

Select the digital filter function and sampling clock by the TRDDFi register.

Figure 16.82 shows a Block Diagram of Digital Filter.

Figure 16.82

Block Diagram of Digital Filter

Clock period selected by

bits TCK2 to TCK0 or

bits DFCK1 to DFCK0

Sampling clock

TRDIOji input signal

Input signal through

digital filtering

Transmission cannot be

performed without 3-time match

because the input signal is

assumed to be noise.

Signal transmission delayed

up to 5-sampling clock

Recognition of the

signal change with

3-time match

i = 0 or 1, j = either A, B, C, or D

TCK0 to TCK2: Bits in TRDCRi register

DFCK0 to DFCK1 and DFj: Bits in TRDDF register

IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register

IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register

Latch

Match

detection

circuit

Edge detection

circuit

DFj

Sampling clock

IOA2 to IOA0

IOB2 to IOB0

IOC3 to IOC0

IOD3 to IOD0

DFCK1 to DFCK0

TRDIOji input signal

f32

Latch

Timer RD operation clock

f1, fOCO40M)

Count source

= 101b

= 100b

= 011b

= 110b

= 010b

= 001b

fOCO40M

f32

TRDCLK

= 000b

= 00b

= 01b

= 10b

= 11b

TCK2 to TCK0

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