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R8C2K bảng dữ liệu(PDF) 372 Page - Renesas Technology Corp |
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R8C2K bảng dữ liệu(HTML) 372 Page - Renesas Technology Corp |
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372 / 471 page ![]() R8C/2K Group, R8C/2L Group 19. A/D Converter Rev.1.10 Dec 21, 2007 Page 355 of 450 REJ09B0406-0110 19.2 Repeat Mode In repeat mode, the input voltage of one selected pin is A/D converted repeatedly. Table 19.3 lists the Repeat Mode Specifications. Figures 19.6 and 19.7 show Registers ADCON0 and ADCON1 in Repeat Mode. Table 19.3 Repeat Mode Specifications Item Specification Function The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is A/D converted repeatedly Start conditions • When the ADCAP bit is set to 0 (software trigger): Set the ADST bit to 1 (A/D conversion starts) • When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM mode): A compare match between registers TRD0 and TRDGRA0 or a TRD1 underflow is generated while the ADST bit is set to 1 Stop condition Set the ADST bit to 0 Interrupt request generation timing Not generated Input pin Select one of AN2, AN4 to AN11 Reading of result of A/D converter Read AD register |
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