R8C2K datasheet(359/471 Pages) RENESAS

359 / 471 page

R8C/2K Group, R8C/2L Group

18. Hardware LIN

Rev.1.10

Dec 21, 2007

Page 342 of 450

REJ09B0406-0110

Figure 18.9

Example of Header Field Reception Flowchart (2)

Timer RA Set to start a pulse width measurement

TSTART bit in the TRACR register

← 1

Timer RA Read the count status flag

TCSTF flag in the TRACR register

Hardware LIN Set to start Synch Break detection

LSTART bit in the LINCR register

← 1

Hardware LIN Read the RXD0 input status flag

RXDSF flag in the LINCR register

TCSTF = 1 ?

YES

RXDSF = 1 ?

YES

Timer RA waits until the timer starts

counting.

Hardware LIN Clear the status flags

(Bus collision detection, Synch Break

detection, Synch Field measurement)

Bits B2CLR, B1CLR, B0CLR in the LINST

← 1

Hardware LIN Read the Synch Break detection flag

SBDCT flag in the LINST register

SBDCT = 1 ?

YES

Do not apply “L” level to the RXD pin

until the RXDSF flag reads 1 after

writing 1 to the LSTART bit. This is

because the signal applied during this

time is input directly to UART0.

Three to five cycles of the CPU clock

are required after the LSTART bit is set

to 1 before the RXDSF flag is set to 1.

After this, input to timer RA and UART0

is enabled.

Hardware LIN detects a Synch Break.

The interrupt of the timer RA may be

used.

Hardware LIN waits until the RXD0

input for UART0 is masked.

When Synch Break is detected, timer

RA is reloaded with the initially set

count value.

Even if the duration of the input “L”

level is shorter than the set period,

timer RA is reloaded with the initially

set count value and waits until the

next “L” level is input.

Three to five cycles of the CPU clock

are required after Synch Break

detection before the SBDCT flag is

set to 1.

When the SBE bit in the LINCR

Synch Break is detected), timer RA

can be used in timer mode after the

SBDCT flag in the LINST register is

set to 1 and the RXDSF flag is set to

Zero to one cycle of the timer RA count

source is required after timer RA starts

counting before the TCSTF flag is set to

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