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SH7149 bảng dữ liệu(PDF) 55 Page - Renesas Technology Corp

tên linh kiện SH7149
Giải thích chi tiết về linh kiện  32-Bit RISC Microcomputer SuperH??RISC engine Family
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7149 bảng dữ liệu(HTML) 55 Page - Renesas Technology Corp

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Section 1 Overview
Rev. 3.00 May 17, 2007 Page 11 of 974
REJ09B0229-0300
Classification
Symbol
I/O
Name
Function
RES
I
Power-on reset
When low, this LSI enters the power-
on reset state.
MRES
I
Manual reset
When low, this LSI enters the
manual reset state.
WDTOVF
O
Watchdog timer
overflow
Output signal for the watchdog timer
overflow. If this pin needs to be
pulled down, use the resistor larger
than 1 M
Ω to pull this pin down.
BREQ
I
Bus-mastership
request
Low when an external device
requests the release of the bus
mastership.
This pin is not available in the
SH7146.
System control
BACK
O
Bus-mastership
request
acknowledge
Indicates that the bus mastership
has been released to an external
device. Reception of the
BACK
signal informs the device which has
output the
BREQ signal that it has
acquired the bus.
This pin is not available in the
SH7146.
NMI
I
Non-maskable
interrupt
Non-maskable interrupt request pin.
Fix to high or low level when not in
use.
Interrupts
IRQ3 to IRQ0 I
Interrupt requests
3 to 0
Maskable interrupt request pin.
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
IRQOUT
O
Interrupt request
output
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release
state.
Address bus
A19 to A0
O
Address bus
Outputs addresses.
No address bus pins are available in
the SH7146.
Data bus
D15 to D0
I/O
Data bus
16-bit bidirectional bus.
No data bus pins are available in the
SH7146.



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