STV9432TA datasheet(20/24 Pages) STMICROELECTRONICS

20 / 24 page

STV9432TA

20/24

Locking Condition Time Constant (@ 4035)

This register provides the AS[2:0] and BS[2:0]

constants used by the algo part of the PLL (see

Figure 10). These two constants as well as the

phase error (err(n)) give the new value (Dn) of the

high frequency signal division. Consequently,

AS[2:0] and BS[2:0] fix the pixel clock frequency.

These two constants are used only in locking con-

dition, if the phase error is inferior to a fixed value

during at least 4 scan lines. If the phase error

becomes superior to the fixed value, the PLL is

not in locking condition but in capture process. In

this case, the algo part of the PLL uses the other

constants AF[2:0] and BF[2:0] from the next regis-

ter.

Capture Process Time Constant (@ 4036)

The choice between these two time constants

(locking condition or capture process) allows to

decrease the capture process time by changing

the time response of the PLL.

10.5.2 - How to choose the time constant value

The time response of the PLL is given by its char-

acteristic equation which is:

(x - 1)2 + (

) . (x - 1) +

= 0

Where:

[6:1] . 2A -11 and

= 3 . LD[6:1] . 2B - 19

(LD[6:1] = value of the LINE DURATION register,

A = value of the 1st time constant, AF or AS and

B = value of the 2d time constant, BF or BS).

As can be seen, the solution depends only on the

LINE DURATION and the TIME CONSTANTS

given by the I2C registers.

If (

)2 - 4

and 2

< 4, the PLL is sta-

ble and its response is as shown in Figure 15.

If (

)2 - 4

, the response of the PLL is as

shown in Figure 13. In this case the PLL is stable

> 0.7 damping coefficient.

Table 3 gives some good values for A and B con-

stants for different values of the LINE DURATION.

Figure

12.

Time

Response

the

PLL/

Characteristic equation solutions (with real

solutions)

Figure

13.

Time

Response

the

PLL/

Characteristic

equation

solutions

(with

complex solutions)

Table 3

Valid Time Constants Examples

Case of A[2:0] = 1 (001) and B[2:0] = 4 (100)

:Table meaning: N = No possible capture - No stability, Y = PLL can lock.

αβ

3LD

⋅

αβ

β 0

≥α β

–

αβ

β 0

≤

PLL Frequency

Input Frequency

PLL Frequency

Input Frequency

B \ A

YYYY

YYYN

YNNN

NNNN

YYYY

YYYN

YNNN

NNNN

NYYY

YYYY

YYYN

YNNN

NNNN

NNNY

YYYY

YYYN

YNNN

NNNN

NYYY(1)

YYYY

YYYN

YNNN

NNNN

NNNY

YYYY

YYYN

YNNN

NNNN

NYYY

YYYN

YNNN

NNNN

NNNY

YYYN

YNNN

NNNN

LD[6:1]

Valid Time Constants

NYYY

STV9432TA bảng dữ liệu(PDF) 20 Page - STMicroelectronics

STV9432TA bảng dữ liệu(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL