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STV7697A bảng dữ liệu(PDF) 10 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  PLASMA DISPLAY PANEL SCAN DRIVER
PDF  15 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STV7697A bảng dữ liệu(HTML) 10 Page - STMicroelectronics

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STV7697A
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AC TIMINGS REQUIREMENTS
(VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR,tF) = 10 ns)
AC TIMINGS CHARACTERISTICS
(VCC =5 V, VPP =90 V, VSSP =0 V, VSSLOG =VSSSUB =0 V, Tamb =25°C, fCLK = 20 MHz, VILMax. = 0.2
Vcc, VIHMin. = 0.8 VCC,VOH = 4.0 V, VOL = 0.4 V, CL = 15pF, unless otherwise specified)
Note 7 One output among 64, loading capacitor COUT = 100pF, other outputs at low level.
Symbol
Parameter
Min.
Typ.
Max.
Unit
tCLK
Data Clock Period
50
-
-
ns
tWHCLK
Duration of clock (CLK) pulse at high level
15
-
-
ns
tWHCLK
Duration of clock (CLK) pulse at low level
15
-
-
ns
tSDAT
Set-up Time of data input before clock low to high transition
10
-
-
ns
tHDAT
Hold Time of data input after clock low to high transition
10
-
-
ns
tSFR
Forward/reverse (F/R) Set-up Time before low to high transition
100
-
-
ns
tDSTB
Minimum Delay to latch STB after clock low to high transition
10
-
-
ns
tSTB
Strobe STB Pulse Duration
20
-
-
ns
tBLK
Blank (BLK) Pulse Duration
500
-
-
ns
tPOL
Polarity (POL) Pulse Duration
500
-
-
ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
tCLK
Data Clock Period
50
-
-
ns
tRDAT
tFDAT
Logical Data Output Rise Time
Logical Data Output Fall Time
-
-
20
11
-
-
ns
ns
tPHL1
tPLH1
Delay of logic data output after clock (CLK) high to low transition
Delay of logic data output after clock (CLK) low to high transition
-
-
45
48
80
80
ns
ns
tPHL2
tPLH2
Delay of power output change after clock (CLK) high to low transition
Delay of power output change after clock (CLK) low to high transition
-
-
120
120
180
180
ns
ns
tPHL3
tPLH3
Delay of power output change after blanking (BLK) high to low transition
Delay of power output change after blanking (BLK) low to high transition
-
-
110
110
165
165
ns
ns
tPHL4
tPLH4
Delay of power output change after polarity (POL) high to low transition
Delay of power output change after polarity (POL) low to high transition
-
-
-
-
160
160
ns
ns
tROUT
tFOUT
Power Output Rise Time (7)
Power Output Fall Time (7)
-
-
100
60
200
200
ns
ns
3



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