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HD74AC74P bảng dữ liệu(PDF) 1 Page - Renesas Technology Corp |
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HD74AC74P bảng dữ liệu(HTML) 1 Page - Renesas Technology Corp |
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1 / 8 page ![]() Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC74 Dual D-Type Positive Edge-Triggered Flip-Flop REJ03D0277–0200Z (Previous ADE-205-361 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Features Asynchronous Inputs: Low input to S D (Set) sets Q to High level Low input to C D (Clear) sets Q to Low level Clear and Set are independent of clock Simultaneous Low on C D and SD makes both Q and Q High • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC74P DIP-14 pin DP-14, -14AV P — HD74AC74FPEL SOP-14 pin (JEITA) FP-14DAV FP EL (2,000 pcs/reel) HD74AC74RPEL SOP-14 pin (JEDEC) FP-14DNV RP EL (2,500 pcs/reel) HD74AC74TELL TSSOP-14 pin TTP-14DV T ELL (2,000 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement 1 2 3 4 5 6 7 CD1 D1 CP1 SD1 Q1 Q1 GND VCC CD2 D2 CP2 SD2 Q2 Q2 14 13 12 11 10 9 8 CP1 CP2 SD1 CD2 SD2 CD1 D1 D2 Q1 Q2 (Top view) Q2 Q1 |
Số phần tương tự - HD74AC74P |
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Mô tả tương tự - HD74AC74P |
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