Jitter trap

Since the internally generated serial clock is locked

to the incoming parallel clock, there exists periodic

jitter components which are generated from the

phase comparison process of the PLL.

A serial resonant circuit (trap) connected between

frequency reduces effectively the fundamental

component of the jitter well below the specification

(

±0.25ns).

Recommended values of C1 and L1 are given in

the following table.

RECOMMENDED VALUES OF THE TRAP CIRCUIT

COMPONENT

STANDARD

D1

D2

PAL

NTSC

C1 (pF)

150

240

300

L1 (

µH)

0.2

0.3

0.4

An important remark in a practical implementation

is that TRP node is an input of a very sensitive

voltage-frequency converter (VCO) which can be

easily disturbed by any pick-up noise.

Hence, the trap circuit should be carefully located

and be kept as short as possible from the Pin 34 in

order to avoid noise problems.

V

EE

STV1601A

10k

Ω

TN1

35

33

36

FV

Small signal

transistor

Frequency monitor

10

µF

22k

Ω

1k

Ω

PCK

TRP

34

C1

L1

Figure 20 : VCO Temperature Compensation and Free Running Adjustment

Time scale

NRZI signal

NRZ signal

NRZI signal

NRZI inverted signal

NRZ to NRZI conversion

NRZ to NRZI conve rsion

Figure 19 : Relation between NRZ and NRZI Signals

STV1601A

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