7546 datasheet(64/95 Pages) RENESAS

64 / 95 page

7546 Group

Rev.1.21

Nov 15, 2006

page 64 of 93

REJ03B0160-0121

Fig. 80 State transition 2

Operation clock source: On-chip oscillator (Note 2)

Operation clock source: f(XIN) (Note 1)

Notes on switch of clock

(1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio.

f(XIN)/2 (High-speed mode)

f(XIN)/8 (Middle-speed mode)

f(XIN) (Double-speed mode, only at a ceramic oscillation)

(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.

ROSC/1 (On-chip oscillator double-speed mode)

ROSC/2 (On-chip oscillator high-speed mode)

ROSC/8 (On-chip oscillator middle-speed mode)

ROSC/128 (On-chip oscillator low-speed mode)

(3) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation.

(4) After system is released from reset, and state transition of state 2

→ state 3 and state transition of state 2’ → state 3’,

ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.

(5) MCU cannot be returned by On-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected.

Accordingly, do not execute the transition to state 2'a.

(6) STP instruction cannot be used when oscillation stop detection circuit is in active.

RESET state 2

f(XIN) oscillation: enabled

On-chip oscillator: enabled

RESET state 1

f(XIN) oscillation: enabled

On-chip oscillator: enabled

Oscillation stop detection circuit is in active. (Note 6)

Applied “L” to RESET pin

(external reset)

MISRG3 is cleared to “0”.

MISRG2=12

MISRG2=02

MISRG2=12

MISRG2=02

MISRG1=12

MISRG1=02

(MISRG3 is cleared to “0”.)

MISRG1=12

(Note 3)

MISRG1=02

(MISRG3 is cleared to “0”.)

State 3

State 2

f(XIN) oscillation: enabled

On-chip oscillator: enabled

f(XIN) oscillation: enabled

On-chip oscillator: enabled

State 3’

State 2’

f(XIN) oscillation: enabled

On-chip oscillator: enabled

State 2’a (Note 5)

Oscillation stop reset disabled

When oscillation stop is detected;

MISRG3 is set to “1”.

Internal RESET does not occur.

Prohibitive state

MUC will be locked when Ceramic

or RC oscillation is stopped.

State 3’a

Oscillation stop reset disabled

When oscillation stop is detected;

MISRG3 is set to “1”.

Internal RESET does not occur.

Oscillation stop reset enabled

When oscillation stop is detected;

MISRG3 is set to “1”.

Internal RESET occurs.

Oscillation stop reset enabled

When oscillation stop is detected;

MISRG3 is set to “1”.

Internal RESET occurs.

State 3’c

Release from internal reset

MISRG3 is set to “1”.

Oscillation status can be

confirmed by reading MISRG3.

f(XIN) oscillation: enabled

On-chip oscillator: enabled

State 3’b

State 2’b

CPUM76=102

(Note 4)

CPUM76=002

012

112

(Note 3)

CPUM76=102

CPUM76=002

012

112

CPUM76=102

(Note 4)

CPUM76=002

012

112

Reset

released

(Note 4)

Reset

released

(Note 4)

Oscillation stop is detected

(internal reset)

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