7470 datasheet(21/47 Pages) RENESAS

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7470/7471 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

A-D CONVERTER

The A-D conversion uses an 8-bit successive comparison method.

Figure 11 shows a block diagram of the A-D conversion circuit.

Conversion is automatically carried out once started by the pro-

gram.

There are eight analog input pins which are shared with P20 to

P27 of port P2 (Only P20 to P23 4-bit for 7470 group. Which ana-

log inputs are to be A-D converted is specified by using bit 2 to bit

0 in the A-D control register (address 00D916). Pins for inputs to

be A-D converted must be set for input by setting the direction reg-

ister bit to “0”. Bit 3 in the A-D control register is an A-D conversion

end bit. This is “0” during A-D conversion; it is set to “1” when the

conversion is terminated. Therefore, it is possible to know whether

A-D conversion is terminated by checking this bit. Bit 4 in the A-D

control register is a VREF connection selection bit.

During A-D conversion, this bit must be set “1” for the ladder resis-

tor and VREF pin to be connected; after the A-D conversion is

terminated, this bit can be reset to “0” to separate the ladder resis-

tor from the VREF pin. In this way, power consumption in the ladder

resistor can be suppressed while no A-D conversion is performed.

Figure 13 shows the relationship between the contents of A-D

control register and the selected input pins.

The A-D conversion register (address 00DA16) contains informa-

tion on the results of conversion, so that it is possible to know the

results of conversion by reading the contents of this register.

The following explains the procedure to execute A-D conversion.

First, set values to bit 2 to bit 0 in the A-D control register to select

the pins that you want to execute A-D conversion. Next, clear the

A-D conversion end bit to “0”.

When the above is done, A-D conversion is initiated. The A-D con-

version is completed after an elapse of 50 machine cycles

(12.5

µs when f(XIN)= 8 MHz), the A-D conversion end bit is set to

“1”, and the interrupt request bit is set to “1”. The results of conver-

sion are contained in the A-D conversion register.

Fig. 11 A-D converter circuit

Comparator

A-D control circuit

Switch tree

Ladder resistor

A-D conversion completion

interrupt request

VSS (Note 1)

VREF

1 : AVSS for M37471M2/M4/M8/E4/E8-XXXFP

2 : 7470 group does not have P2 4/IN4 to P27/IN7 pins.

P20/IN0

P21/IN1

P22/IN2

P23/IN3

P24/IN4

P25/IN5

P26/IN6

P27/IN7

Data bus

A-D control register

(Address 00D916)

bit 4

Notes

bit 0

A-D conversion register

(Address 00DA16)

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