M37151MA datasheet(97/138 Pages) RENESAS

97 / 138 page

M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP

Rev.1.00

Nov 01, 2002

page 97 of 136

REJ03B0129-0100Z

8.15 OSD CLOCK GENERATING CIRCUIT

When generate OSD clock based on main clock, connect capacity to

FILT pin.

Set bit 0 of the clock control register 1 (address 00CD16) to operate

OSD clock generating circuit “0.” Clock control register 1 (address

00CD16) is shown in Fig.8.15.3. Then, clock frequency for OSD is set

up by the clock frequency register (address 021016).

Clock frequency setting register is shown in Fig.8.15.2.

Fig.8.15.1 Display Oscillation Circuit

FLIT

Table.8.15.1 OSD Clock frequency

Clock frequency

setting register

(address 021016)

OSD clock

frequency

26 MHz

28 MHz

In order to generate normally oscillation frequency for OSD shown in

Table 8.15.1, be sure to set the main clock f (XIN) to 8MHz. Then, set

up not any values other than these.

Fig.8.15.3 Clock Control Register 1

Clock control register 1

Clock control register 1 (CC1) [Address 00CD16]

b7 b6 b5 b4 b3 b2 b1 b0

000

System clock generating

circuit control bit (CC10)

0: Operation

1: Stop

Fix these bits to "0"

1 to

Name

BFunctions

After reset R W

R W

Fig.8.15.2 Clock Frequency Register

Clock frequency set register(CFS) [Address 021016]

Clock frequency set register

0 to

b7 b6 b5 b4 b3 b2 b1 b0

Clock frequency bit

(CFS 0 to 7)

Clock frequency (Note)

Setting value(Limitation)

Frequency(MHz)

Name

BFunctions

After reset R W

R W

Note: Do not set other than the values shown above to CFS.

Then, must to use at f(XIN) = 8 MHz.

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