3825 datasheet(21/71 Pages) RENESAS

21 / 71 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3825 Group

Fig. 15 Port block diagram (2)

(9) Ports P55, P57

Data bus

Pull-up control

CNTR1 interrupt input

A-D trigger interrupt input

Direction

Port latch

(10) Port P6

Data bus

Pull-up control

Direction

Port latch

A-D conversion input

Analog input pin selection bit

(13) Port P80

Data bus

Port Xc switch bit + Pull-up control

Port XC switch bit

Oscillation circuit

Port P81

Port XC switch bit

Direction

Port latch

(15) COM0–COM3

VL3

VL2

VL1

The gate input signal of each

transistor is controlled by the

LCD duty ratio and the bias

value.

VSS

(16) SEG0–SEG17

The voltage applied to the sources of

P-channel and N-channel transistors

is the controlled voltage by the bias

value.

VL2/VL3

VL1/VSS

Pulse output mode

CNTR0 interrupt input

Timer output

Direction

Port latch

Data bus

P54 only

(11) Port P70

(12) Ports P71–P77

Data bus

Direction

Port latch

(14) Port P81

Data bus

Port XC switch bit

Sub-clock generating circuit input

Direction

Port latch

Pull-up control

Data bus

Pull-up control

(8) Ports P54, P56

Port Xc switch bit + Pull-up control

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