HD404618TF datasheet(47/91 Pages) RENESAS

47 / 91 page

HD404618 Series

System

clock

INT1

Selector

Prescaler S (PSS)

Clock

Timer counter register BU (TCBU)

Timer counter

(TCBL)

Timer counter B

(TCB)

Timer load

(TLRU)

Timer load

(TLRL)

Timer mode

(TMB)

Timer B interrupt

request flag

(IFTB)

fcyc/fSUB

(tcyc/tsubcyc)

Free-running

control

Overflow

Figure 27 Timer B Block Diagram

Timer C (TCCL and TCRL: $00E, TCCU and TCRU: $00F): Eight-bit write-only timer load register

(TCRL and TCRU) and read-only timer counter (TCCL and TCCU) located at the same addresses. The

eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. The

operation of timer C is basically the same as that of timer B.

The auto-reload function and prescaler division ratio of timer C depend on the state of timer mode register

C (TMC). Timer C is initialized to the value set in TMC by software, and is then incremented by one at

each clock input. If an input is applied to timer C after it has reached $FF, an overflow is generated. In

this case, if the auto-reload function is enabled, timer C is initialized to its initial value; if auto-reload is

disabled, the timer is initialized to $00. The overflow sets the timer C interrupt request flag (IFTC: $002,

bit 2).

Timer C also functions as a watchdog timer. If a program routine runs out of control and an overflow is

generated while the watchdog on (WDON) flag is set, the MCU is reset. This error can be detected by

having the program control timer C reset before timer C reaches $FF.

The WDON can only have 1 written to it ; it is cleared to 0 only by MCU reset.

Timer Mode Register A (TMA: $008): Four-bit write-only register that controls timer A as shown in

table 21.

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