HD404328 datasheet(13/96 Pages) RENESAS

13 / 96 page

HD404328 Series

Bit 3

Bit 2

Bit 1

Bit 0

IM0

(IM of

INT )

IMTA

(IM of timer A)

IMTC

(IM of timer C)

IMAD

(IM of A/D)

IF0

(IF of

INT )

IFTA

(IF of timer A)

IFTC

(IF of timer C)

IFAD

(IF of A/D)

RSP

(Reset SP bit)

IM1

(IM of INT )

IMTB

(IM of timer B)

IMZC

(IM of ZCD)

(Interrupt enable flag)

IF1

(IF of INT )

IFTB

(IF of timer B)

IFZC

(IF of ZCD)

DTON

(Direct transfer on flag)

ADSF

(A/D start flag)

WDON

(Watchdog on flag)

LSON

(Low speed on flag)

IMS

(IM of serial interface)

IFS

(IF of serial interface)

IF:

IM:

IE:

SP:

Interrupt request flag

Interrupt mask

Interrupt enable flag

Stack pointer

Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD instruction,

reset by the REM or REMD instruction, and tested by the TM or TMD instruction. Other

instructions have no effect.

However, note the following usage limitations of RAM bit manipulation instructions.

$000

$001

$002

$003

$020

$021

$022

$023

Not used

SEM/SEMD

Not executed

Allowed

Not executed in active mode

Used in subactive mode

REM/REMD

Allowed

Not executed

Allowed

TM/TMD

Allowed

Inhibited

Allowed

RSP

WDON

DTON

Note: WDON is reset by MCU reset.

DTON is always reset in active mode.

If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes invalid.

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

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