HD151TS201AT datasheet(19/29 Pages) RENESAS

19 / 29 page

HD151TS201AT

Rev.1.00, Oct.21.2003, page 19 of 28

Pin Descriptions (cont.)

Pin name

No.

Type

Description

REF

OUTPUT

14.318MHz reference clock.

MULT0

INPUT

CPUCLK’s output current setting.

This pin is 150k

Ω internal pull-up.

PWRDWN#

INPUT

Power down pin. All circuits will be powered down.

(Output state of each output is shown in page Table.)

Asynchronous active low input pin used to power down the

device into low power state. The internal clocks are disabled

and VCO and the crystal are stopped.

USB48

OUTPUT

3.3V 48 MHz USB clock output.

DOT48

OUTPUT

3.3V 48MHz DOT clock output.

XIN

INPUT

XTAL input.

XOUT

OUTPUT

XTAL output. Don’t connect when an external clock is applied to

XIN.

SDATA

INPUT/

OUTPUT

Data input/output for I

2C logic.

This pin is internal pull-up to VDD by 150K

Ω resistor.

SCLK

INPUT

Clock input for I

2C logic.

This pin is internal pull-up to VDD by 150K

Ω resistor.

IREF

A precision resistor is attached to this pin which is connected to

internal current reference. A resistor is connected between this

pin and GNDIREF.

3V66_0

OUTPUT

3.3 V 66 MHz clock.

3V66_1/VCH

OUTPUT

3.3V clock output selectable with SM Bus byte0, bit5.

When Byte0 bit5 is at logic”1”, this pin is 48 MHz clock output.

When Byte0 bit5 is at logic”0”, this pin is 66 MHz clock output.

Default is 66 MHz output.

66IN/3V66_5

IN/OUT

If S2 = 1, Input connection for 66OUT [2:0].

If S2 = 0, outputs fixed 66 MHz clock.

66OUT[2:0]/

3V66[4:2]

23,22,21

OUTPUT

If S2 = 1, Buffered copies of 66IN.

If S2=0, outputs fixed 66MHz clock.

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