M38264EBFS datasheet(88/91 Pages) RENESAS

88 / 91 page

Rev.1.00

Sep 06, 2006

page 88 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

3.3.15 Notes on standby function

(1) Once the STP instruction is disabled by the STP instruction disable bit (bit 6 of watchdog timer

control register (address 3716)), the microcomputer cannot be return to the STP instruction enable

state.

(2) When using the standby function, note the following.

The power dissipation may increase depending on functions and pin states.

Take the following countermeasures for reduce the power dissipation.

■Countermeasures for reduce power dissipation

•Input ports: Fix to “H” or “L” externally

•Output ports: Fix to level that avoid leak-current.

(Example: Fix the pin to “H“ when the circuit which current flows and LED turns on at “L”

output.)

•A/D input pins: Fix to “H” or “L” externally

•PWMi function enable bits (bits 1 and 2 of PWM control register (address 2B16)): “0”

•LCD enable bit: “0”

•Complete A/D conversion

(Confirm the AD conversion completion bit (bit 3 of AD control register (address 3416)) is “1”)

•VREF input switch bit (bit 4 of AD control register): “0”

•D/Ai conversion register (addresses 3216, 3316): “0016”

(3) When using stop mode

■Operation after restoration by occurrence of interrupt request

•All the timer 123 mode register bits are automatically set to “0” except for bit 4.

•When an interrupt request occurs in the stop mode, the stop mode is released and the clock

stopped by STP starts the oscillation. The oscillation stabilizing time of main clock is secured

to restoration from the stop mode when both the main and sub clocks are oscillating and the

main clock is set for the system clock when executing the STP instruction. Note that the

oscillation of sub clock may not be stable after main clock oscillation being stable.

■When LCD display

Execute the STP instruction after turning LCD to OFF by setting the LCD enable bit (bit 3 of

LCD mode register (address 3916)) to “0”. If the STP instruction is executed while the LCD is

ON, direct voltage will be applied to the LCD panel.

■Watchdog timer

The watchdog timer stops during the stop mode but operates during the oscillation stabilizing

time. Therefore, the watchdog timer control register must be written just before executing the

STP instruction to prevent its underflow.

(4) When using wait mode

■Restoration by reset input

When the sub clock is selected as the system clock and the main clock is stopped at the time

WIT instruction is executed, if the RESET pin input level is set to “L”, the sub clock oscillation

stops and the main clock oscillation starts. Oscillation is unstable at first and requires an

oscillation stabilizing time. Retain the RESET pin input level at “L” until the oscillation is stabilized.

After the oscillation has stabilized, retain the RESET pin at “L” for 2 µs or more in order to set

the internal reset state.

■Watchdog timer

The watchdog timer operates during the wait mode. The watchdog timer control register must

be written to prevent its underflow.

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