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M3826AE4FS bảng dữ liệu(PDF) 78 Page - Renesas Technology Corp |
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M3826AE4FS bảng dữ liệu(HTML) 78 Page - Renesas Technology Corp |
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78 / 91 page  Rev.1.00 Sep 06, 2006 page 78 of 88 REJ03B0181-0100 3826 Group (One Time PROM version) (3) Timers 1–3 Set the value of timer in the order of the timer 1 register, the timer 2 register, and the timer 3 register after the count source selection of timer 1 to 3. <Reason> •When the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. •If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. (4) Timer 2 If the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the high-order register and the underflow of timer 2 are performed at the same timing. (5) All timers ■The count source for timers is effected by system clock φ which is selected by the system clock selection bit (bit 7 of CPU mode register (address 3B16)). ■Set the timer which is not used as follows: •Stop the count (when using a timer with stop control) •Set “0” to the corresponding interrupt enable bit |
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