M38265EBGP datasheet(57/91 Pages) RENESAS

57 / 91 page

Rev.1.00

Sep 06, 2006

page 57 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”. Af-

ter a reset, initialize flags (T flag, D flag, etc.) which affect program

execution.

Interrupt

When the contents of an interrupt request bits are changed by the

program, execute a BBC or BBS instruction after at least one in-

struction. This is for preventing executing a BBC or BBS

instruction to the contents before change.

Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to

“1”, then execute an ADC or SBC instruction. After executing an

ADC or SBC instruction, execute at least one instruction before

executing a SEC, CLC, or CLD instruction.

In decimal mode, the values of the negative (N), overflow (V), and

zero (Z) flags are invalid.

Multiplication and Division Instructions

The index mode (T) and the decimal mode (D) flags do not affect

the MUL and DIV instruction.

The execution of these instructions does not change the contents

of the processor status register.

Ports

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

The contents of the port direction registers cannot be read.

The following cannot be used:

• LDA instruction

• The memory operation instruction when the T flag is “1”

• The bit-test instruction (BBC or BBS, etc.)

• The read-modify-write instruction (calculation instruction such as

ROR etc., bit manipulation instruction such as CLB or SEB etc.)

• The addressing mode which uses the value of a direction regis-

ter as an index

Serial I/O

In clock synchronous serial I/O, if the receive side is using an ex-

ternal clock and it is to output the SRDY signal, set the transmit en-

able bit, the receive enable bit, and the SRDY output enable bit to

“1”.

The TxD pin of serial I/O1 retains the level then after transmission

is completed.

In serial I/O2 selecting an internal clock, the SOUT2 pin goes to

high impedance state after transmission is completed.

In serial I/O2 selecting an external clock, the SOUT2 pin retains the

level then after transmission is completed.

A/D Converter

The input to the comparator is combined by internal capacitors.

Therefore, since conversion accuracy may be worse by losing of

an electric charge when the conversion speed is not enough,

make sure that f(XIN) is at least 500 kHz during an A/D conver-

sion.

The normal operation of A/D conversion cannot be guaranteed

when performing the next operation:

•When writing to CPU mode register during A/D conversion op-

eration

•When writing to AD control register during A/D conversion op-

eration

•When executing STP instruction or WIT instruction during A/D

conversion operation

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the system clock φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The frequency of the system clock φ depends on the main clock

division ratio selection bit and the system clock selection bit.

M38265EBGP bảng dữ liệu(PDF) 57 Page - Renesas Technology Corp

M38265EBGP bảng dữ liệu(HTML) 57 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

bảng dữ liệu tải về

Link URL