M38261EBGP datasheet(28/91 Pages) RENESAS

28 / 91 page

Rev.1.00

Sep 06, 2006

page 28 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

Timer Y

Timer Y is a 16-bit timer and is equipped with the timer latch. The

division ratio of timer Y is given by 1/(n+1), where n is the value in

the timer latch. Timer Y is a down-counter. When the contents of

timer Y reach “000016”, an underflow occurs at the next count

pulse and the contents of the timer latch are reloaded into the

timer and the count is continued. When the timer underflows, the

timer Y interrupt request bit is set to “1”.

Timer Y can be selected in one of four modes by the timer Y mode

(1) Timer mode

The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

(2) Period measurement mode

CNTR1 interrupt request is generated at rising or falling edge of

CNTR1 pin input signal. Simultaneously, the value in timer Y latch

is reloaded in timer Y and timer Y continues counting down.

Except for this, the operation in period measurement mode is the

same as in timer mode.

The timer value just before the reloading at rising or falling of

CNTR1 pin input signal is retained until the next valid edge is

input.

The rising or falling timing of CNTR1 pin input signal can be

discriminated by CNTR1 interrupt. When using a timer in this

mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port

P5 direction register).

(3) Event counter mode

The timer counts signals input through the CNTR1 pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the

P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction

(4) Pulse width HL continuously measure-

ment mode

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal. Except for this, the operation in

pulse width HL continuously measurement mode is the same as in

period measurement mode. When using a timer in this mode, set

the P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5

direction register).

■Note on CNTR1 interrupt active edge selection

CNTR1 interrupt active edge depends on the value of the CNTR1

active edge switch bit. However, in pulse width HL continuously

measurement mode, CNTR1 interrupt request is generated at both

rising and falling edges of CNTR1 pin input signal regardless of

the value of CNTR1 active edge switch bit.

Fig. 24 Structure of timer Y mode register

Timer Y mode register

(TYM : address 002816)

Not used (“0” at reading)

Timer Y operating mode bits

b5b4

00 : Timer mode

01 : Period measurement mode

10 : Event counter mode

11 : Pulse width HL continuously

measurement mode

CNTR1 active edge switch bit

0 : Count at rising edge in event counter mode

Measure the falling edge to falling edge

period in period measurement mode

Falling edge active for CNTR1 interrupt

1 : Count at falling edge in event counter mode

Measure the rising edge period in period

measurement mode

Rising edge active for CNTR1 interrupt

Timer Y stop control bit

0 : Count start

1 : Count stop

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