M38260EBGP datasheet(67/91 Pages) RENESAS

67 / 91 page

Rev.1.00

Sep 06, 2006

page 67 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

SWITCHING CHARACTERISTICS

Table 26 Switching characteristics 1

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)

Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

0.2 ✕ tC (SCLK2)

Symbol

Parameter

Limits

Min.

Unit

tC (SCLK1)/2–30

–30

Typ.

Max.

twH(SCLK1)

twL(SCLK1)

td(SCLK1–TXD)

tv(SCLK1–TXD)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

td(SCLK2–SOUT2)

tv(SCLK2–SOUT2)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Table 27 Switching characteristics 2

(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)

Unit

Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

0.2 ✕ tC (SCLK2)

Symbol

Parameter

Limits

Min.

tC (SCLK1)/2–50

–30

Max.

twH(SCLK1)

twL(SCLK1)

td(SCLK1–TXD)

tv(SCLK1–TXD)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

td(SCLK2–SOUT2)

tv(SCLK2–SOUT2)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Typ.

tC (SCLK2)/2–160

tC (SCLK2)/2–240

Fig. 69 Circuit for measuring output switching characteristics

Measurement output pin

100 pF

CMOS output

Note: When P71–P77, P40 and bit 4 of the UART control

drain output mode).

N-channel open-drain output (Note)

1 kΩ

100 pF

Measurement output pin

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