M38262EBFP datasheet(44/91 Pages) RENESAS

44 / 91 page

Rev.1.00

Sep 06, 2006

page 44 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

LCD DRIVE CONTROL CIRCUIT

The 3826 group has the Liquid Crystal Display (LCD) drive control

circuit consisting of the following.

•LCD display RAM

•Segment output enable register

•LCD mode register

•Voltage multiplier

•Selector

•Timing controller

•Common driver

•Segment driver

•Bias control circuit

A maximum of 40 segment output pins and 4 common output pins

can be used.

Up to 160 pixels can be controlled for LCD display. When the LCD

Fig. 46 Structure of segment output enable register and LCD mode register

enable bit is set to “1” (LCD ON) after data is set in the LCD mode

RAM, the LCD drive control circuit starts reading the display data

automatically, performs the bias control and the duty ratio control,

and displays the data on the LCD panel.

Table 11 Maximum number of display pixels at each duty ratio

Duty ratio

Maximum number of display pixel

80 dots

or 8 segment LCD 10 digits

120 dots

or 8 segment LCD 15 digits

160 dots

or 8 segment LCD 20 digits

Segment output enable bit 0

0 : Output ports P30–P35

1 : Segment output SEG18–SEG23

Segment output enable bit 1

0 : Output ports P36, P37

1 : Segment output SEG24,SEG25

Segment output enable bit 2

0 : I/O ports P00–P05

1 : Segment output SEG26–SEG31

Segment output enable bit 3

0 : I/O ports P06,P07

1 : Segment output SEG32,SEG33

Segment output enable bit 4

0 : I/O port P10

1 : Segment output SEG34

Segment output enable bit 5

0 : I/O ports P11–P15

1 : Segment output SEG35–SEG39

LCD output enable bit

0 : Disabled

1 : Enabled

Not used (“0” at reading)

(Write “0” to this bit at writing.)

Segment output enable register

(SEG : address 003816)

LCD mode register

(LM : address 003916)

Duty ratio selection bits

b1b0

0 0 : Not used

0 1 : 2 duty (use COM0, COM1)

1 0 : 3 duty (use COM0–COM2)

1 1 : 4 duty (use COM0–COM3)

Bias control bit

0 : 1/3 bias

1 : 1/2 bias

LCD enable bit

0 : LCD OFF

1 : LCD ON

Voltage multiplier control bit

0 : Voltage multiplier disable

1 : Voltage multiplier enable

LCD circuit divider division ratio selection bits

b6b5

0 0 : Clock input

0 1 : 2 division of Clock input

1 0 : 4 division of Clock input

1 1 : 8 division of Clock input

LCDCK count source selection bit (Note)

0 : f(XCIN)/32

1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)

Note : LCDCK is a clock for a LCD timing controller.

M38262EBFP bảng dữ liệu(PDF) 44 Page - Renesas Technology Corp

M38262EBFP bảng dữ liệu(HTML) 44 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

bảng dữ liệu tải về

Link URL