M38039G4HKP datasheet(31/92 Pages) RENESAS

31 / 92 page

Rev.1.10

Nov 14, 2005

Page 31 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 21. Block diagram of timer X, timer Y, timer 1, and timer 2

“1”

“0”

P54/CNTR0

P55/CNTR1

“0”

“1”

“0”

“1”

Prescaler X latch (8)

Prescaler X (8)

Timer X latch (8)

Timer X (8)

To timer X interrupt

request bit

Toggle flip-flop

Timer X count stop bit

Pulse width

measurement

mode

Event

counter

mode

To CNTR0 interrupt

request bit

Pulse output mode

Port P54

latch

Port P54

direction register

CNTR0 active

edge switch bit

Timer X latch write pulse

Pulse output mode

Timer mode

Pulse output mode

Prescaler Y latch (8)

Prescaler Y (8)

Timer Y latch (8)

Timer Y (8)

To timer Y interrupt

request bit

Toggle flip-flop

Timer Y count stop bit

To CNTR1 interrupt

request bit

Pulse output mode

Port P55

latch

Port P55

direction register

CNTR1 active

edge switch bit

Timer Y latch write pulse

Pulse output mode

Timer mode

Pulse output mode

Prescaler 12 latch (8)

Prescaler 12 (8)

Timer 1 latch (8)

Timer 1 (8)

Timer 2 latch (8)

Timer 2 (8)

To timer 2 interrupt

request bit

To timer 1 interrupt

request bit

CNTR0 active

edge switch bit

CNTR1 active

edge switch bit

Pulse width

measurement

mode

Event

counter

mode

Clock for timer 12

Data bus

XIN

(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)

Divider

Count source

selection bit

Main clock

division ratio

selection bits

“00”

“11”

“10”

XCIN

f(XCIN)

Count source selection bit

f(XCIN)

Clock for timer Y

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