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32C8B bảng dữ liệu(PDF) 19 Page - Renesas Technology Corp |
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32C8B bảng dữ liệu(HTML) 19 Page - Renesas Technology Corp |
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19 / 69 page ![]() M32C/8B Group 2. Central Processing Unit (CPU) REJ03B0242-0050 Rev.0.50 Oct 31, 2008 Page 19 of 67 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 2.1 General Registers 2.1.1 Data Registers (R0, R1, R2, and R3) R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1. 2.1.2 Address Registers (A0 and A1) A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations. 2.1.3 Static Base Register (SB) SB is a 24-bit register used for SB-relative addressing. 2.1.4 Frame Base Register (FB) FB is a 24-bit register used for FB-relative addressing. 2.1.5 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently. 2.1.6 Interrupt Table Register (INTB) INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table. 2.1.7 Program Counter (PC) PC is 24 bits wide and indicates the address of the next instruction to be executed. 2.1.8 Flag Register (FLG) FLG is a 16-bit register indicating the CPU state. 2.1.8.1 Carry Flag (C) The C flag indicates whether or not carry or borrow has been generated after executing an instruction. 2.1.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.1.8.3 Zero Flag (Z) The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0. 2.1.8.4 Sign Flag (S) The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0. 2.1.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1. 2.1.8.6 Overflow Flag (O) The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0. |
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