HD74LS669

Rev.2.00, Feb.18.2005, page 6 of 8

Waveforms 1

Clock

Load

Data Inputs

A, B, C, D

Enable

P

or

Enable

T

Up/

Down

Enable

T

Input

Ripple

Carry

Output

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

0V

3V

0V

3V

0V

3V

0V

3V

0V

3V

0V

3V

10% 10%

90%

90%

Notes:

1.

2.

Propagation delay time from up / douwn to ripple carry must be measured with the counter at

either aminimum or a maximum count. As the logic level of the up / down input is changed, the

riiple carry output will follow. If the count is minimum (0) are ripple carry output transition will

be in phase. If the count is macimum (15) the ripple carry output will be out of phase.

3.

≤ 15 ns, t

THL

≤ 6 ns, PRR = 1 MHz