HD151BF854

Rev.5.00 Apr 07, 2006 page 2 of 7

Pin Arrangement

1

2

3

4

5

6

7

8

9

10

Y0

Y0

VDD

Y1

Y1

GND

NC

CLKIN

AVDD

AGND

VDD

Y2

Y2

NC

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Y3

Y3

FBOUT

FBIN

NC

NC

VDD

Y4

Y5

GND

Y5

GND

NC

Y4

(Top view)

Pin Functions

Pin name

No.

Type

Description

AGND

11

Ground

Analog ground. AGND provides the ground reference for the analog circuitry.

AVDD

10

Power

Analog power supply. AVDD provides the power reference for the analog

circuitry. In addition, AVDD can be used to bypass the PLL for test purposes.

When AVDD is strapped to ground, PLL is bypassed and CLK is buffered

directly to the device outputs.

CLKIN

8

Input

Clock input. CLKIN provides the clock signal to be distributed by the

HD151BF854 clock buffer. CLK is used to provide the reference signal to the

integrated PLL that generates the clock output signals. CLK must have a

fixed frequency and fixed phase for the PLL to obtain phase lock. Once the

circuit is powered up and a valid CLK signal is applied, a stabilization time is

required for the PLL to phase lock the feedback signal to its reference signal.

FBIN

20

Input

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN

must be hard-wired to FBOUT to complete the PLL. The integrated PLL

synchronizes CLKIN and FBIN so that there is nominally zero phase error

between CLKIN and FBIN.

FBOUT

19

Output

Feedback output. FBOUT is dedicated for external feedback. It switches at

the same frequency as CLK. When externally wired to FBIN, FBOUT

completes the feedback loop of the PLL.

GND

6, 15, 28

Ground

Ground

VDD

3, 12, 23

Power

Power supply

Y

2, 4, 13,

17, 24, 26

Output

Clock outputs. (+Clock) These outputs provide low-skew copies of CLK.

Y

1, 5, 14,

16, 25, 27

Output

Bar clock outputs. (–Clock) These outputs provide low-skew copies of CLK.

NC

7, 9, 18, 21,

22

NC

Don’t connect any VDD or GND.