33911 datasheet(38/45 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33911

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

Timing Control Register - TIMCR

This register is a double purpose register which allows to

configure the watchdog and the cyclic sense periods. Writing

to the Timing Control Register (TIMCR) will also return the

Watchdog Status Register (WDSR).

CS/WD - Cyclic Sense or Watchdog prescaler select.

This write-only bit selects which prescaler is being written

to, the Cyclic Sense prescaler or the watchdog prescaler.

1 = Cyclic Sense Prescaler selected

0 = watchdog Prescaler select

WDx - Watchdog Prescaler

This write-only bits selects the divider for the watchdog

prescaler and therefore selects the watchdog period in

accordance with Table 22. This configuration is valid only if

windowing watchdog is active.

Table 22. Watchdog Prescaler

CYSTx - Cyclic Sense Period Prescaler Select

This write-only bits selects the interval for the wake-up

cyclic sensing together with the bit CYSX8 in the

Configuration Register (CFR) (see page 39).

This option is only active if the high side switch is enabled

when entering in Stop or Sleep Mode. Otherwise a timed

wake-up is performed after the period shown in Table 23.

Table 23. Cyclic Sense Interval

Watchdog Status Register - WDSR

This register returns the watchdog status information and

is also returned when writing to the TIMCR.

WDTO - Watchdog Timeout

This read-only bit signals the last reset was caused by

either a watchdog timeout or by an attempt to clear the

watchdog within the window closed.

Any access to this register or the TIMCR will clear the

WDTO bit.

1 = Last reset caused by watchdog timeout

0 = None

Table 21. Timing Control Register - $A

Write

CS/WD

WD2

WD1

WD0

CYST2

CYST1

CYST0

Reset

Value

000

Reset

Condition

-POR

WD2

WD1

WD0

Prescaler Divider

CYSX8(59)

CYST2

CYST1

CYST0

Interval

No cyclic sense

20ms

40ms

60ms

80ms

100ms

120ms

140ms

160ms

320ms

480ms

640ms

800ms

960ms

1120ms

Notes

59.

bit CYSX8 is located in Configuration Register (CFR)

Table 24. Watchdog Status Register - $A/$B

Read

WDTO

WDERR

WDOFF

WDWO

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