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STCF03ITBR bảng dữ liệu(PDF) 18 Page - STMicroelectronics

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Introduction
STCF03I
18/33
The register address byte determines the first register in which the read or write operation
takes place. When the read or write operation is finished, the register address is
automatically increased.
7.10
Writing to multiple registers with incremental addressing
It would be unpractical to send several times the device address and the address of the
register when writing to multiple registers. STCF03I supports writing to multiple registers
with incremental addressing. When data is written to a register, the address register is
automatically increased, so the next data can be sent without sending the device address
and the register address again. See Figure 10 below.
7.11
Reading from a single register
The reading operation starts with a START bit followed by the 7 bit device address of
STCF03I. The 8th bit is the R/W bit, which is 0 in this case. STCF03I confirms the receiving
of the address + R/W bit by an acknowledge pulse. The address of the register which should
be read is sent afterwards and confirmed again by an acknowledge pulse of STCF03I again.
Then the master generates a START bit again and sends the device address followed by the
R/W bit, which is 1 now. STCF03I confirms the receiving of the address + R/W bit by an
acknowledge pulse and starts to send the data to the master. No acknowledge pulse from
the master is required after receiving the data. Then the master generates a STOP bit to
terminate the communication. See Figure 11
Figure 10.
Writing to multiple registers with incremental addressing
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER i
DATA i
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER i
DATA i
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER i
DATA i
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
SDA LINE



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