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33742S bảng dữ liệu(PDF) 51 Page - Freescale Semiconductor, Inc |
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33742S bảng dữ liệu(HTML) 51 Page - Freescale Semiconductor, Inc |
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51 / 70 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 51 33742 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS WAKE-UP REGISTER (WUR) Tables 27 through 29 contain the Wake-up Register information. Local wake-up inputs L0:L3 can be used in both Normal and Standby modes as port expander, as well as for waking up the SBC from Sleep or Stop modes (Table 27). Wake-up inputs can be configured by pair. L0 and L1 can be configured together, and L1 and L2, and L2 and L3 can be configured together (Table 28). Table 25. HSON Control Bits Logic HS State 0 HS OFF, in Normal and Standby modes. 1 HS ON, in Normal and Standby modes.(60) Notes 60. When HS is turned OFF due to an over-temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error bits are latched in the IOR register. Table 26. Input/Output Register Status Bits Name Logic Description V2LOW 0 V2LTH > 4.0V. 1 V2LTH < 4.0V. HSOT 0 No HS over-temperature. 1 HS over-temperature. VSUPLOW 0 VBF(EW) > 5.8V. 1 VBF(EW) < 5.8V. DEBUG 0 SBC not in Debug mode. 1 SBC accepts command to go to Debug modes (no Watchdog). Table 27. Wake-Up Register WUR R/W D3 D2 D1 D0 $100b W LCTR3 LCTR2 LCTR1 LCTR0 R L3WU L2WU L1WU L0WU Reset Value – 0 0 0 0 Reset Condition (Write)(61) – POR, NR2R, N2R, STB2R, STO2R Notes 61. See Table 13, page 47, for definitions of reset conditions. |
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