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M34D64WMN6P bảng dữ liệu(PDF) 12 Page - STMicroelectronics

tên linh kiện M34D64WMN6P
Giải thích chi tiết về linh kiện  64 Kbit serial I²C bus EEPROM with hardware write control on top quarter of memory
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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M34D64WMN6P bảng dữ liệu(HTML) 12 Page - STMicroelectronics

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Device operation
M34D64-W
12/27
3
Device operation
The device supports the I2C protocol. This is summarized in Figure 6.: I2C bus protocol. Any
device that sends data on to the bus is defined to be a transmitter, and any device that reads
the data to be a receiver. The device that controls the data transfer is known as the bus
master, and the other as the slave device. A data transfer can only be initiated by the bus
master, which will also provide the serial clock for synchronization. The M34D64-W device is
always a slave in all communications.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal EEPROM Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.



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