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L5987 - L5987A

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6.4.1

Type III compensation network

The methodology to stabilize the loop consists of placing two zeros to compensate the effect

of the LC double pole, so increasing phase margin; then to place one pole in the origin to

minimize the dc error on regulated output voltage; finally to place other poles far away the

zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a

frequency higher than the desired bandwidth (that is: 2

π∗ESR∗COUT<1/BW), the type III

compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR

(<1 m

Ω), with very high frequency zero, so type III network is adopted to compensate the

loop.

In Figure 10 the type III compensation network is shown. This network introduces two zeros

(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:

Equation 20

Equation 21

Figure 10.

Type III compensation network

In Figure 11 the bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))

and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.

π C

()

⋅⋅

------------------------------------------------

π R

⋅⋅

------------------------------

π R

⋅⋅

------------------------------

π R

⋅

--------------------

⋅⋅

--------------------------------------------

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