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STPC12GDYI bảng dữ liệu(PDF) 98 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  X86 Core PC Compatible System-on-Chip for Terminals
PDF  111 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STPC12GDYI bảng dữ liệu(HTML) 98 Page - STMicroelectronics

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DESIGN GUIDELINES
98/111
Issue 1.0 - July 24, 2002
6.4.4. PCI INTERFACE
6.4.4.1. Introduction
In order to achieve a PCI interface which work at
clock
frequencies
up
to
33MHz,
careful
consideration has to be given to the timing of the
interface with all the various electrical and
physical constraints taken into consideration.
6.4.4.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T0 and T1.
Figure 6-28. Clock Scheme
HCLK PLL
1/2
1/3
1/4
clock
Strap Options
PCICLKO
T1
PCICLKI
HCLK
AD[31:0]
South
North
Deskewer
MUX
T0
T2
delay
STPC
MD[30:27]
MD[17,4]
MD[7:6]
Bridge
Bridge



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