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STPCC0366BTC3 bảng dữ liệu(PDF) 42 Page - STMicroelectronics |
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STPCC0366BTC3 bảng dữ liệu(HTML) 42 Page - STMicroelectronics |
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42 / 51 page ![]() BOARD LAYOUT 42/51 Release B This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 6.2 High speed signals Some Interfaces of the STPC run at high speed and have to be carefully routed or even shielded. Here is the list of these interfaces, in decreasing speed order: 1) Memory Interface. 2) Graphics and video interfaces 3) PCI bus 4) 14MHz oscillator stage All the clocks haves to be routed first and shielded for speeds of 27MHz or more. The high speed sig- nals follow the same contrainsts, like the memory control signals and the PCI control signals. The next interfaces to be routed are Memory, Vid- eo/graphics, and PCI. All the analog noise sensitive signals have to be routed in a separate area and hence can be rout- ed indepedently. Figure 6-8. Shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines |
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