STPCC4HEBC datasheet(40/93 Pages) STMICROELECTRONICS

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40 / 93 page

ELECTRICAL SPECIFICATIONS

40/93

Release 1.5 - January 29, 2002

4.5.3. SDRAM INTERFACE

Figure 4-5, Table 4-10 lists the AC characteristics

of the SDRAM interface.

For correct operation, the programmable read

clock delay (RDCLK) must be activated for the

CRTC and the delay set to the minimum. This is

done by setting the Latch_CRTC_Data_In bit in

the SDRAM Controller register 0 and clear the

bits[3:0] in register 1.

The PC133 memory is recommended to reach

100MHz operation.

Figure 4-5. SDRAM Timing Diagram

MCLKI

STPC.output

STPC.input

MCLKx

Tdelay

Tsetup

Thold

Toutput (min)

Toutput (max)

Tcycle

Thigh

Tlow

Table 4-10. SDRAM Bus AC Timing

Name

Parameter

Min

Typ

Max

Unit

Tcycle

MCLKI Cycle Time

Thigh

MCLKI High Time

Tlow

MCLKI Low Time

MCLKI Rising Time

MCLKI Falling Time

Tdelay

MCLKx to MCLKI delay

-0.9

Toutput

MCLKI to Outputs Valid

5.2

MCLKI to DQM[ ] Outputs Valid

6.5

8.8

MCLKI to MD[ ] Outputs Valid

6.5

8.8

Tsetup

MD[63:0] setup to MCKLI

3.75

4.0

Thold

MD[63:0] hold from MCKLI

1.3

2.5

Note: These timing are for a load of 50pF.

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